The University of New South Wales

Microarchitectural timing channels and their prevention on an open-source 64-bit RISC-V core

Authors

Nils Wistoff, Moritz Schneider, Frank Gürkaynak, Luca Benini and Gernot Heiser

DATA61

ETH Zurich

UNSW Sydney

Best Paper Award

Abstract

Microarchitectural timing channels use variations in the timing of events, resulting from competition for limited hardware resources, to leak information in violation of the operating system’s security policy. Such channels also exist on a simple in-order RISC-V core, as we demonstrate on the open- source RV64GC Ariane core. Time protection, recently proposed and implemented in the seL4 microkernel, aims to prevent timing channels, but depends on a controlled reset of microarchitectural state. Using Ariane, we show that software techniques for performing such a reset are insufficient and highly inefficient. We demonstrate that adding a single flush instruction is sufficient to close all five evaluated channels at negligible hardware costs, while requiring only minor modifications to the software stack.

BibTeX Entry

  @inproceedings{Wistoff_SGBH_21,
    publisher        = {IEEE},
    booktitle        = {Design, Automation and Test in Europe (DATE)},
    month            = feb,
    paperurl         = {https://trustworthy.systems/publications/csiro_full_text/Wistoff_SGBH_21.pdf},
    year             = {2021},
    title            = {Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit {RISC}-{V} Core},
    numpages         = {6},
    author           = {Wistoff, Nils and Schneider, Moritz and G\"{u}rkaynak, Frank and Benini, Luca and Heiser, Gernot},
    address          = {virtual},
    date             = {2021-2-1}
  }

Download