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Seminar;2015-08-19: Gorka Irazoqui on Prevention of microarchitectural side channel attacks in the cloud
Side channel attacks have shown to be a potential thread for co-resident virtual machines in cloud computing environments. Among all, last level cache side channel attacks have proved to be the most powerful ones, being able to extract fine grain information such as cryptographic keys. Due to the increasing success of these kind of attacks, protections have to be implemented against them. In this work, we are building a tool that can mitigate side channel attacks in cloud environments. This is implemented in two steps: first, an identification phase where we detect that a malicious VM is running a side channel attack, and second, mitigate the attack by changing the memory layout of the malicious VM. For the identification phase, Hardware Performance Counters will be analysed looking for expected patterns for cache side channel attacks. In the mitigation phase, we will move malicious VM's memory pages to form a moving target defence. Although the tool will be applied to detect cache based side channel attacks, we believe it could also be adapted to detect microarchitectural attacks that use different hardware resources. This is work in progress.

Seminar;2015-08-19: Gorka Irazoqui on Prevention of microarchitectural side channel attacks in the cloud

Side channel attacks have shown to be a potential thread for co-resident virtual machines in cloud computing environments. Among all, last level cache side channel attacks have proved to be the most powerful ones, being able to extract fine grain information such as cryptographic keys. Due to the increasing success of these kind of attacks, protections have to be implemented against them. In this work, we are building a tool that can mitigate side channel attacks in cloud environments. This is implemented in two steps: first, an identification phase where we detect that a malicious VM is running a side channel attack, and second, mitigate the attack by changing the memory layout of the malicious VM. For the identification phase, Hardware Performance Counters will be analysed looking for expected patterns for cache side channel attacks. In the mitigation phase, we will move malicious VM's memory pages to form a moving target defence. Although the tool will be applied to detect cache based side channel attacks, we believe it could also be adapted to detect microarchitectural attacks that use different hardware resources. This is work in progress.

Seminar 2015-08-19:Tom Allan; Mobile code cache-based side-channel attacks
Side-channel attacks have been shown to leak cryptographic keys. However, for the attack, the adversary needs access to the physical machine the victim executes on. So, the question is how does the adversary gets her code to the victim machine. Web-based mobile code provides an easy vector for getting code to the target machine, however there are several hurdles for implementing such attacks from mobile code. The first hurdle is that the attack code executes within a virtual address space which hides the mapping of the cache. Past research relies on huge pages to recover this mapping, however huge pages are not available to mobile code. We describe a cache profiling technique that allows us to profile the cache without the use of huge pages. Another hurdle is that cache-based attacks rely on a high-resolution timer. As a precaution against cache-based attacks, browsers are now moving towards disabling high-resolution timers. We demonstrate that we can create a high-resolution timer by using multiple threads. Lastly, prior cache-based attacks focused on statically-compiled languages. With the move to the Web, many programs are now written in dynamic languages. Consequently the memory layout of the program is unknown to the adversary. We show that implementations in dynamic languages are still vulnerable. We implement the attack code in both Javascript and as Google Chrome's Native Client. We use the attack against the Javascript ElGamal encryption as implemented in Openpgp.js and show that using the side channel information we can reduce the search space to 2^30 keys.

Seminar 2015-08-19:Tom Allan; Mobile code cache-based side-channel attacks

Side-channel attacks have been shown to leak cryptographic keys. However, for the attack, the adversary needs access to the physical machine the victim executes on. So, the question is how does the adversary gets her code to the victim machine. Web-based mobile code provides an easy vector for getting code to the target machine, however there are several hurdles for implementing such attacks from mobile code.

The first hurdle is that the attack code executes within a virtual address space which hides the mapping of the cache. Past research relies on huge pages to recover this mapping, however huge pages are not available to mobile code. We describe a cache profiling technique that allows us to profile the cache without the use of huge pages.

Another hurdle is that cache-based attacks rely on a high-resolution timer. As a precaution against cache-based attacks, browsers are now moving towards disabling high-resolution timers. We demonstrate that we can create a high-resolution timer by using multiple threads. Lastly, prior cache-based attacks focused on statically-compiled languages. With the move to the Web, many programs are now written in dynamic languages. Consequently the memory layout of the program is unknown to the adversary. We show that implementations in dynamic languages are still vulnerable.

We implement the attack code in both Javascript and as Google Chrome's Native Client. We use the attack against the Javascript ElGamal encryption as implemented in Openpgp.js and show that using the side channel information we can reduce the search space to 2^30 keys.

Seminar 2015-08-18: Harry Butterworth on Paxos In Production
The core of IBM's Spectrum Virtualize(TM) software is a Paxos-based, fault-tolerant cluster operating environment which has been in production use since 2003. In the context of multinational enterprise IT infrastructure, I will first introduce some current storage products powered by IBM Spectrum Virtualize(TM) software, then I will review fault-tolerance and the Paxos protocol and finally I will describe a programming model, protocol extensions, supporting features and optimizations used in this deployment of Paxos in production.

Seminar 2015-08-18: Harry Butterworth on Paxos In Production

The core of IBM's Spectrum Virtualize(TM) software is a Paxos-based, fault-tolerant cluster operating environment which has been in production use since 2003. In the context of multinational enterprise IT infrastructure, I will first introduce some current storage products powered by IBM Spectrum Virtualize(TM) software, then I will review fault-tolerance and the Paxos protocol and finally I will describe a programming model, protocol extensions, supporting features and optimizations used in this deployment of Paxos in production.

2015-08-17 Best Scientific Cybersecurity Paper Award Winner
Congratulations to TS's Prof Carroll Morgan and co-authors, who have won the Annual NSA Best Scientific Cybersecurity Paper Award for their paper Additive and Multiplicative Notions of Leakage and Their Capacities published at last year's IEEE Computer Security Foundations Symposium.

Seminar 2015-08-17: Jan Auer; Enhancing Static Analysis with Runtime Verification
Static program analysis and runtime verification are two complementary, yet supplemental approaches to ensuring correct program execution. Theformer is well established and integrated in many development environments, as well as several enterprise-grade standalone tools. Runtime verification, on the other hand, facilitates targeted monitoring of production systems without the risk of false positives or false negatives. In this presentation we preset "Static Runtime Verification", a formalbridge between static analysis and runtime verification that leverages synergy effects between both approaches. Analysis comprises three stages: Identification of error candidates using static analysis, event instrumentation at these locations, and final runtime monitoring. Moreover, we introduce our prototype platform StaticRV and a number of use cases

Seminar 2015-08-17: Jan Auer; Enhancing Static Analysis with Runtime Verification

Static program analysis and runtime verification are two complementary, yet supplemental approaches to ensuring correct program execution. Theformer is well established and integrated in many development environments, as well as several enterprise-grade standalone tools. Runtime verification, on the other hand, facilitates targeted monitoring of production systems without the risk of false positives or false negatives. In this presentation we preset "Static Runtime Verification", a formalbridge between static analysis and runtime verification that leverages synergy effects between both approaches. Analysis comprises three stages: Identification of error candidates using static analysis, event instrumentation at these locations, and final runtime monitoring. Moreover, we introduce our prototype platform StaticRV and a number of use cases

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