PLEB 2

PLEB 2 is a single board computer designed to provide a platform on which both academic research and application implementation can be accomplished. It has been based on PLEB. Design documents were drafted in January, 2003, and the first operating system was booted some time later, in September 2004.

PLEB 2 is a 100mmx70mm board based on an Intel XScale PXA255 processor. It has 32MB of on-board RAM, and 8MB flash.

See the HOWTO for information on how to perform common operations on PLEB2.

Hardware

CPU Board

PLEB 2 is based on the XScale PXA255 applications processor from Intel. This device provides a high-performance ARMv5TE core running at up to 400MHz, with a large number of internal peripherals including (but not limited to): an LCD controller, UART(s), PCMCIA, memory/DMA controller, AC97, infra-red communications, I2S, I2C, and MMC. See the PXA255 developer's manual for further details

SDRAM and Flash devices are situated on-board (initial devices give 32MB and 8MB respectively). The PXA255, SDRAM and Flash memory constitute the core of the system. In addition to this, a microcontroller is used to supervise the main processor. The microcontroller is used to: provide remote reset, measure power consumption on the system's power supplies, configure some hardware aspects of the board and provide a ready-to-use JTAG interface.

The system is capable of running off a single Li-ION or Li-Polymer battery between 3.3 and 4.2V. An on-board power supply and battery charger can accept a higher voltage (up to 16V DC), which eliminates the need for a battery should it not be required. The power supply is dynamically adjustable in order to perform scaling of the processor's core voltage.

Peripherals connected on-board include a miniature USB connector connected to the USB-client interface of the PXA255, two push-buttons, an IrDA transceiver, and a RS232 port.

PLEB 2 is designed to be adapted via two mechanisms. Two 100-pin connectors allow daughtercards to be stacked above the CPU board. Virtually all useable signals from the PXA255 are exported to these connectors. A scheme has been developed whereby the CPU can identify which daughtercards are connected and in which order, as well as allocating limited resources (e.g. interrupt request lines, etc). Power can be provided by the daughtercard to the CPU board, as well as from the CPU-board to the daughtercard. The connectors provide an 8mm spacing.

A side-card connector provides access to a small, useful subset of the connections on the daughtercard connectors, as well as the AVR and CPU RS232 ports and direct access to the JTAG lines for an external debugger. This is intended for quick-and-nasty projects, as well as access to the device's serial ports without the use of a daughter card.

The PCB measures 100mm x 70mm (the same dimensions as a 2.5" hard disk drive). Four holes provide for physical mounting.

Network/IDE/USB Host Board

Software support

Bootloader

The U-Boot bootloader was chosen because of its tidy code-base and full feature-set. It was ported to PLEB 2. All basic features work well, including manipulation of and writing to the flash memory. It is suspected that when the Network/IDE/USB Host board becomes available, the bootloader will support booting from the network (via TFTP), and from a hard-disk.

U-boot supports the passing of kernel parameters to Linux, along with the storage of an initial ram-disk.

Boot parameters are stored in flash memory and can be re-written by the bootloader.

Operating system

For further information email daves.pleb 'at' cse.unsw.edu.au.