A new virtual memory implementation for L4/MIPS
Authors
Cristan Szmajda
School of Computer Science and Engineering
UNSW,
Sydney 2052, Australia
Abstract
Title: A New Virtual Memory Implementation for L4/MIPS
Author: Cristan Szmajda
School of Computer Science and Engineering,
The University of New South Wales, Sydney 2052, Australia,
cls@cse.unsw.edu.au
Abstract:
This thesis adapts a new data structure, the level and path compressed
trie, for use as a page table. Path compression is a technique also
applied in the guarded page table, used in the present implementation
of the L4/MIPS micro-kernel. Level compression is a recent technique
which reduces the depth of guarded page tables so that page table
look-up in dense address space distributions can potentially be
reduced to only one or two array indexing operations.
Like hierarchical page tables, the GPT and LPC trie have natural
support for super-pages provided by newer architectures. Support for
super-pages increases the coverage of the hardware TLB, decreasing the
frequency of TLB misses. The new structure will replace the current
virtual memory sub-system of the L4/MIPS micro-kernel. The principle
L4/MIPS data structures are also re-designed for efficiency and
reduced memory usage. The new implementation is substantially simpler
and is designed to be safe in pre-emptable and SMP kernels.
BibTeX Entry
@mastersthesis{Szmajda:be,
address = {Sydney, Australia},
author = {Cristan Szmajda},
keywords = {GPT, Patricia trie, level compression, path compression, varibale node size, multiple page sizes},
month = nov,
note = {Available from publications page at \url{http://ts.data61.csiro.au/}},
paperUrl = {https://trustworthy.systems/publications/theses_public/99/Szmajda%3Abe.ps.gz},
school = {School of Computer Science and Engineering},
title = {A New Virtual Memory Implementation for {L4/MIPS}},
year = {1999}
}
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